VHDL Implementation of Optimized Cascaded Integrator Comb (CIC) Filters for Ultra High Speed Wideband Rate Conversion

Software defined radio (SDR) is a radio in which the properties of carrier frequency, signal bandwidth, modulation, and several other characteristics are defined by software. Today's SDR is turning the hardware problems into software problems, some or all of the physical layer functions are software defined. Digital down conversion (DDC) and Digital up conversion (DUC) is one of the core technologies in SDR, as well as an important component of digital intermediate frequency (IF) receiver system. Cascade Integrator Comb (CIC) filters are widely used in multirate signal processing as a filter in both decimator (decrease in the sampling rate) and interpolator (increase in the sampling rate). In this paper a CIC filter, an optimized class of linear filters is implemented for digital up conversion (DUC) and digital down conversion (DDC) for efficient transmission and reception in Software Defined Radio (SDR) communication system. In this project a full-fledged digital down conversion and digital up conversion systems are developed in VHDL for FPGA based software defined radio applications. The CIC based architecture is implemented in VHDL and will be tested on Xilinx FPGAs. All the modules functionality is verified with Modelsim simulator. Xilinx ISE tools are used for FPGA synthesis, Place & Route and timing analysis. Spartan 3E development board with Chipscope Pro Analyzer tool is used for on-chip verification.